A_Gmr (General Mode Register); A_Gsr (General Status Register) - NEC uPD98502 User Manual

4.4.2 A_GMR (General Mode Register)

A_GMR is used to select operation mode of this block, enables/disables ATM SAR operations. After reset,
V 4120A must write this register for initialization. Modification of A_GMR after starting Tx/Rx operations is prohibited.
R
All bits of this register are writeable, but the bits 31-15, 13-2 are reserved for future use. Initial value is all zero.
Bits Field
31:15 Reserved
14 LP
13:2 Reserved
1 TE
0 RE

4.4.3 A_GSR (General Status Register)

A_GSR shows interruption status. When an event that triggers interruption occurs, F/W on RISC Core set a bit in
A_GSR corresponds to the type of event. If the corresponding bit in A_IMR (Interrupt Mask Register) is set to a '0' and
the interruption is not masked, an interruption is issued to V
When the same type of events occurs before the bit has been read, the bit will be set again.
Initial value is all zero.
Bits Field
31 PI
30 RQA
29 RQU
28:24 Reserved
23 SQO
22 Reserved
21 FER
20:17 Reserved
16 BER
15:8 RCR[7:0]
7:4 MF[3:0]
3:0 MM[3:0]
240
CHAPTER 4 ATM CELL PROCESSOR
R/W Default
R/W 0 Reserved for future use. Write '0's.
R/W 0 0 = Loopback is not performed at the UTOPIA interface
1 = Loopback is performed at the UTOPIA interface
R/W 0 Reserved for future use. Write '0's.
R/W 0 0 = Transmit disable
1 = Transmit enable
R/W 0 0 = Receive disable
1 = Receive enable
R/W Default
RC 0 0 = PHY layer device interruption has not occurred
1 = PHY layer device interruption has occurred
RC 0 0 = receive Queue alert has not occurred
1 = receive Queue alert has occurred
RC 0 0 = receive Queue underflow has not occurred
1 = receive Queue underflow has occurred
R 0 Reserved for future use
RC 0 0 = scheduling Queue overflow has not occurred
1 = scheduling Queue overflow has occurred
R 0 Reserved for future use
RC 0 0 = Fatal Error has not occurred
1 = Fatal Error has occurred
R 0 Reserved for future use
RC 0 0 = Internal Bus Error has not occurred
1 = Internal Bus Error has occurred
RC 0 0 = raw cell is not in Pool No. [7:0]
1 = raw cell is in Pool No. [7:0]
RC 0 0 = Mailbox No. [3:0] is not full
1 = Mailbox No. [3:0] is full
RC 0 0 = mailbox No. [3:0] is not marked
1 = Mailbox No. [3:0] is marked
Preliminary User's Manual S15543EJ1V0UM
Description
4120A. The bit in A_GSR is able to be read cleared.
R
Description