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LWR
Given a word in a register and a word in memory, the operation of LWR is as follows:
LWR
Register
Memory
Remark LEM
Little-endian memory (BigEndianMem = 0)
Type
AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset
pAddr2..0 sent to memory
S
sign-extend of destination31
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
520
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Word Right (3/3)
A
B
C
I
J
K
vAddr2..0
Destination
0
S S S S MN O P
1
S S S S E M N O
2
S S S S E F M N
3
S S S S E F GM
4
S S S S I J K L
5
S S S S E I J K
6
S S S S E F I J
7
S S S S E F G I
Preliminary User's Manual S15543EJ1V0UM
D
E
F
G
L
M
N
O
Type
Offset
(LEM)
3
0
2
1
1
2
0
3
3
4
2
5
1
6
0
7
LWR
H
P
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