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BC0TL
Branch On Coprocessor 0 True Likely (1/2)
31
26 25
COPz
Note
0 1 0 0 X X
6
Format:
BC0TL offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset , shifted left two bits and sign-extended. If the contents of CP0's condition (CpCond) line, as sampled during
the previous instruction, is true, the target address is branched to with a delay of one instruction.
If the conditional branch is not taken, the instruction in the branch delay slot is nullified.
Because the condition line is sampled during the previous instruction, there must be at least one instruction
between this instruction and a coprocessor instruction that changes the condition line.
Operation:
condition ← SR
32
T-1:
target ← (offset
T:
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
condition ← SR
64
T-1:
target ← (offset
T:
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions:
Coprocessor unusable exception
Note See the opcode table below, or A.6 CPU Instruction Opcode Bit Encoding.
446
APPENDIX A MIPS III INSTRUCTION SET DETAILS
21 20
BC
BCTL
0 1 0 0 0
0 0 0 1 1
5
5
18
14
2
)
|| offset || 0
15
18
46
2
)
|| offset || 0
15
Preliminary User's Manual S15543EJ1V0UM
16 15
BC0TL
offset
16
0
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