Tlt Instruction Pipeline Activities - NEC uPD98502 User Manual

2.3.4.4 Trap if less than instruction (TLT rs, rt)
IF stage Same as the IF stage for the ADD instruction.
RF stage Same as the RF stage for the ADD instruction.
EX stage ALU controls are set to do an A - B operation. The operands flow into the ALU inputs, and the
ALU operation is started. The result of the ALU operation is latched into the ALU output latch
during Φ 1. The sign bits of operands and of the ALU output latch are checked to determine if a
less than condition is true. If this condition is true, a Trap exception occurs. The value in the
PC register is used as an exception vector value, and from now on any instruction will be
invalid.
DC stage No operation
WB stage The value of the PC is loaded to EPC register if the less than condition was met in the EX
stage. The Cause register ExCode field and BD bit are updated appropriately, as is the EXL bit
of the Status register. If the less than condition was not met in the EX stage, no activity occurs
in the WB stage.
PClock
Phase
Cycle
CHAPTER 2 V
Figure 2-16. TLT Instruction Pipeline Activities
PCycle
Φ 1 Φ 2 Φ 1 Φ 2
IF1 IF2 RF1 RF2
IDC ICA
ITLB ITC IDEC RF
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Φ 1 Φ 2 Φ 1 Φ 2
EX1 EX2 DC1 DC2
EX
Φ 1 Φ 2
WB1 WB2
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