NEC uPD98502 User Manual page 579

TLBWR
31 26 25
COP0
CO
0 1 0 0 0 0
1
6 1
Format:
TLBWR
Description:
The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi
and EntryLo registers.
The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
Operation:
32, 64 T: TLB [Random
PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0
Exceptions:
Coprocessor unusable exception
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Write Random TLB Entry
24
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
] ←
5...0
Preliminary User's Manual S15543EJ1V0UM
0
19
TLBWR
6 5 0
TLBWR
0 0 0 1 1 0
6
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