Memory Space - NEC uPD98502 User Manual

4.2 Memory Space

Although the RISC Core in the ATM Cell Processor is a 32-bit MPU, its physical memory space is 24-bit width.
xxFF_FFFFH
xxFF_F000H
xxFF_E 3FFH
xxFF_E 000H
xx80_FFFFH
xx80_0000H
xx40_0000H
xx0F_FFFFH
xx00_0000H
The configuration is shown as Figure 4-6. It contains instruction space, shared memory space, work RAM, internal
memory space, and peripheral space.
V 4120A and RISC Core in the ATM Cell Processor share an external memory space. Shared memory will be
R
implemented by using SDRAM devices. The address in V
notified to RISC Core by setting A_IBBAR (IBUS data Base Address Register). Its capacity depends on the total
capacity of physical memory, but not exceeds 4 MB.
236
CHAPTER 4 ATM CELL PROCESSOR
Figure 4-6. Memory Space from V
R IS C C ore
M em ory S pace
P eripheral
Internal D ata
R A M (1 K B )
W ork R A M &
R egister S pace
S hared
M em ory
(4 M B m ax.)
Instruction
space
Preliminary User's Manual S15543EJ1V0UM
4120A and RISC Core
R
V 4120A R IS C P rocessor
R
M em ory S pace
1001_FFFFH
W ork R A M &
R egister S pace
1001_0000H
7F_FFFF H +
(C ontent of A_IB BA R )
(4 M B m ax.)
40_0000H +
(C ontent of A_IB BA R )
0F_FFFF H +
(C ontent of A_IN B AR )
Instruction
(C ontent of A_IN B AR )
A _IB BA R :IBus data B ase Address R egister
A _IN B A R :Instruction B ase A ddress R egister
4120A memory space will be determined by S/W and
R
S hared
M em ory
space