Table of Contents
Advertisement
BGEZL
Branch On Greater Than Or Equal To Zero Likely
31
26 25
REGIMM
0 0 0 0 0 1
6
Format:
BGEZL rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset , shifted left two bits and sign-extended. If the contents of general register rs are zero or greater when
compared to zero, then the program branches to the target address, with a delay of one instruction. If the
conditional branch is not taken, the instruction in the branch delay slot is nullified.
Operation:
target ← (offset
32
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
target ← (offset
64
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
21 20
16 15
BGEZL
rs
0 0 0 1 1
5
5
14
2
)
|| offset || 0
15
= 0)
31
46
2
)
|| offset || 0
15
= 0)
63
Preliminary User's Manual S15543EJ1V0UM
BGEZL
offset
16
0
453
Advertisement
Table of Contents
