Endian Configuration Table; Endian Translation Table In Endian Converter - NEC uPD98502 User Manual

BIG pin ENDCEN
pin
0 0
0 1
1 0
1 1
Remark V 4120A does not support reverse endian mode.
R
CPU access type
Block 2-word
4-word
Single 1-byte
Single 2-byte
Single 3-byte
Single 4-byte
CPU access type BIG
Any 1
202
CHAPTER 3 SYSTEM CONTROLLER
Table 3-1. Endian Configuration Table
Status register
RE field in V 4120A in V
R
0 LITTLE
0 LITTLE
0 BIG
0 BIG
Table 3-2. Endian Translation Table in Endian Converter
BIG ENDCEN Before translation
1 1 00
01
10
11
1 1 00
01
10
11
1 1 00
01
10
11
1 1 00
01
10
11
1 1 00
01
10
11
ENDCEN Before translation
SysAD[1:0]
0 [31:24][23:16][15:8][7:0]
Preliminary User's Manual S15543EJ1V0UM
Endian Endian
4120A in system controller
R
LITTLE
LITTLE
LITTLE
LITTLE
After translation
SysAD[1:0] SysAD[1:0]
00
01
10
11
11
10
01
00
10
11
00
01
01
00
11
10
00
01
10
11
After translation
[7:0][15:8][23:16][31:24]
Endian converter
operation
Transparent
Transparent
Data swap mode
Address swap mode
Notes
Valid
Invalid
Invalid
Invalid
Valid
Valid
Valid
Valid
Valid
Invalid
Valid
Invalid
Valid
Valid
Invalid
Invalid
Valid
Invalid
Invalid
Invalid
Note
SysAD[1:0]
Byte swap