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Instruction
Doubleword Add
DADDI rt, rs, immediate
Immediate
The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a
64-bit result. The result is stored into register rt.
An exception occurs on the generation of integer overflow.
Doubleword Add
DADDIU rt, rs, immediate
Immediate Unsigned
The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a
64-bit result. The result is stored into register rt.
No exception occurs on the generation of overflow.
Instruction
Add
ADD rd, rs, rt
The contents of registers rs and rt are added together to form a 32-bit result. The result is stored into
register rd. In the 64-bit mode, the operand must be sign extended.
An exception occurs on the generation of integer overflow.
Add Unsigned
ADDU rd, rs, rt
The contents of registers rs and rt are added together to form a 32-bit result. The result is stored into
register rd. In the 64-bit mode, the operand must be sign extended.
No exception occurs on the generation of integer overflow.
Subtract
SUB rd, rs, rt
The contents of register rt are subtracted from the contents of register rs. The 32-bit result is stored
into register rd. In the 64-bit mode, the operand must be sign extended.
An exception occurs on the generation of integer overflow.
Subtract Unsigned
SUBU rd, rs, rt
The contents of register rt are subtracted from the contents of register rs. The 32-bit result is stored
into register rd. In the 64-bit mode, the operand must be sign extended.
No exception occurs on the generation of integer overflow.
Set On Less Than
SLT rd, rs, rt
The contents of registers rs and rt are compared, treating both operands as signed integers.
If the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is
set to 0. The result is stored to register rd.
Set On Less Than
SLTU rd, rs, rt
Unsigned
The contents of registers rs and rt are compared treating both operands as unsigned integers.
If the contents of register rs is less than that of register rt, the result is set to 1; otherwise, the result is
set to 0. The result is stored to register rd.
And
AND rd, rt, rs
The contents of register rs are logical ANDed with that of general register rt bit-wise. The result is
stored to register rd.
Or
OR rd, rt, rs
The contents of register rs are logical ORed with that of general register rt bit-wise. The result is stored
to register rd.
Exclusive Or
XOR rd, rt, rs
The contents of register rs are logical Ex-ORed with that of general register rt bit-wise. The result is
stored to register rd.
Nor
NOR rd, rt, rs
The contents of register rs are logical NORed with that of general register rt bit-wise. The result is
stored to register rd.
72
CHAPTER 2 V
Table 2-7. ALU Immediate Instruction (Extended ISA)
Format and Description
Table 2-8. Three-Operand Type Instruction
Format and Description
Preliminary User's Manual S15543EJ1V0UM
4120A
R
rs
op
op
rs
rt
rt
immediate
funct
rd
sa
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