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BLTZ
31
26 25
REGIMM
0 0 0 0 0 1
6
Format:
BLTZ rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset , shifted left two bits and sign-extended. If the contents of general register rs are smaller than zero, then the
program branches to the target address, with a delay of one instruction.
Operation:
target ← (offset
32
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
endif
target ← (offset
64
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
endif
Exceptions:
None
458
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Branch On Less Than Zero
21 20
16 15
BLTZ
rs
0 0 0 0 0
5
5
14
2
)
|| offset || 0
15
= 1)
31
46
2
)
|| offset || 0
15
= 1)
63
Preliminary User's Manual S15543EJ1V0UM
BLTZ
offset
16
0
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