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SB
31
26 25
SB
1 0 1 0 0 0
6
Format:
SB rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The least-significant byte of register rt is stored at the effective address.
Operation:
vAddr ← ((offset
32
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
byte ← vAddr
data ← GPR [rt]
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
vAddr ← ((offset
64
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
byte ← vAddr
data ← GPR [rt]
StoreMemory (uncached, BYTE, data, pAddr, vAddr, DATA)
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
538
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Store Byte
21 20
base
rt
5
5
16
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian
PSIZE - 1...3
2...0
3
xor BigEndianCPU
2...0
8 * byte
|| 0
63 – 8 * byte...0
48
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian
PSIZE - 1...3
2...0
3
xor BigEndianCPU
2...0
8 * byte
|| 0
63 – 8 * byte...0
Preliminary User's Manual S15543EJ1V0UM
16 15
3
))
3
))
SB
offset
16
0
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