Receiving Sof Packet; Receiving Sof Packet And Updating The Frame Number; Updating Frame Number Automatically; Checking If The Skew Of Sof Arrival Time Is Allowable Of Not - NEC uPD98502 User Manual

Network controller
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6.8 Receiving SOF Packet

USB Controller can receive SOF Packets, and check if Frame Number is incremented correctly.
In addition, USB Controller can detect the timing skew of SOF Packet.

6.8.1 Receiving SOF Packet and updating the Frame Number

After USB Controller receives a SOF Packet, FN field in USB Frame Number/Version Register (Address:
1000_1004H) is updated. After FN field is updated, FW bit (Bit 21) in USB General Status Register 2 (Address:
1000_1018H) is set to a '1'.

6.8.2 Updating Frame Number automatically

If received SOF Packet has incorrect Frame Number, USB Controller can execute one of two processes shown
below.
- USB Controller reflects the incorrect Frame Number to FN field directly.
- USB Controller increments Frame Number automatically and write the incremented value to FN field.
The policy of updating FN field is shown in following table:
Case
Correct SOF
Loss of SOF
Extra SOF
Bit Stuff Error
CRC Error
Incorrect Frame Number
Note AU bit is in the USB General Mode Register (Address: 1000_1000H).

6.8.3 Checking if the skew of SOF arrival time is allowable of not

The allowable SOF skew can be defined by SOFINTVL field in the USB General Mode Register (Address:
1000_1000H).
SOFINTVL field is set to 18H (24 clocks) at default. This is 0.05 % of 48000 clocks (1 msec).
The value of SOFINTVL should be set before the first SOF packet comes.
CHAPTER 6 USB CONTROLLER
Note
AU bit
FN field
0
Just load the received Frame Number
1
Just load the received Frame Number
0
Not updated
1
Increment the current FN
0
Not updated
1
Not updated
0
Just load the received Frame Number
1
Increment the current FN
0
Just load the received Frame Number
1
Increment the current FN
0
Just load the received Frame Number
1
Increment the current FN
Figure 6-30. Allowable Skew for SOF
1 msec
The timing
SOF comes
Preliminary User's Manual S15543EJ1V0UM
USB General Status Register 2
FW bit is set to 1
FW bit is set to 1
SL bit is set to 1
FW bit and SL bit are set to 1
ES bit is set to 1
ES bit is set to 1
FW bit is set to 1
FW bit is set to 1
FW bit is set to 1
FW bit is set to 1
FW bit is set to 1
FW bit is set to 1
Allowable
skew
Allowable
skew
The timing
SOF comes
367

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