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2.4.4 System control coprocessor
The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory
management, address translation, exception processing, and other privileged operations. The CP0 contains the
registers and a 32-entry TLB shown in Figure 2-32. The sections that follow describe how the processor uses each of
the memory management-related registers.
Remark
Each CP0 register has a unique number that identifies it; this number is referred to as the register
number.
EntryHi
31
(See Random register for
0
127/255
LLAddr
17*
Remark
CHAPTER 2 V
Figure 2-32. CP0 Registers and TLB
Used for memory management system
EntryLo0
2*
10*
EntryLo1
3*
TLB
(Safe entries)
TLB Wired boundary.)
TagLo
28*
*: Register number
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Used for exception processing
Index
Context
0*
4*
Random
Count
1*
9*
PageMask
Status
5*
12*
Wired
EPC
6*
14*
PRId
WatchHi
15*
19*
Config
Parity Error
16*
26*
TagHi
29*
BadVAddr
8*
Compare
11*
Cause
13*
WatchLo
18*
XContext
20*
Cache Error
27*
ErrorEPC
30*
117
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