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(2) Raw cell transmission
When host sends the non AAL-5 traffic packet which is not OAM F5 cell, host sets "AAL" bit in the packet
descriptor to a 0 and "PTI" field "0xx" which indicates user data. In this case, ATM Cell Processor doesn't calculate or
add AAL-5 trailer.
If host sets "C10" bit in packet descriptor to a 1, ATM Cell Processor calculates and adds CRC-10 to each cell to
be transmitted.
Header
5 bytes
Generation polynomial of CRC-10 is following:
4
G(x) = 1 + x + x
+ x
4.8.2.4 Transmission indication
For each transmitted packet, ATM Cell Processor writes a send indication as a transmission completion status in
the mailbox. The mailbox used for transmission is mailbox 2 and 3. More specifically, ATM Cell Processor writes a
send indication once all the data in the packet has been read. The issuing of a send indication, therefore, does not
indicate that the sending of the packet to PMD has been completed.
Upon storing a send indication into the mailbox, ATM Cell Processor sets the corresponding MM bit of the A_GSR
register to a 1, and issues an interrupt if it is not masked.
The indication that ATM Cell Processor sends to the host during transmission is of the following format:
E
31
30
E (Error ID)
VC Number
A (for Active)
Packet Queue Pointer
4.8.2.5 Scheduling
ATM Cell Processor holds a scheduling table in which ATM Cell Processor sets the transmitting timings of all active
channels. Transmitting timing is recalculated each time ATM Cell Processor transmits a cell. Transmitting timing is
calculated using line rate and rate information which is set by V
information is written in Tx VC table.
CHAPTER 4 ATM CELL PROCESSOR
Figure 4-29. Raw Cell with CRC-10
46 bytes and 6bits
5
9
10
+ x
+ x
Figure 4-30. Send Indication Format
VC Number
Error ID indicates error condition.
0: Error
1: No error
VC Number used for this VC
If 0, indicates that the VC enters the idle state because the packet descriptor is invalid.
If 1, indicates that the VC is kept active because the next packet descriptor is valid.
Low-order 15 bits of the start address of the packet descriptor which is just transmitted.
Preliminary User's Manual S15543EJ1V0UM
Payload
A
PACKET QUEUE POINTER
16
15
14
4120A prior to the Tx_Ready command. Rate
R
CRC-10
10 bits
0
269
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