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3.7 Endian Mode Software Issues
3.7.1 Overview
The native endian mode for MIPS processors, like Motorola and IBM 370 processors, is big endian. However, the
native mode for Intel (which developed the PCI standard) and VAX processors is little endian. For PCI-compatibility
reasons, most PCI peripheral chips operate natively in little-endian mode. While the µ PD98502 is natively little-endian,
it supports either big- or little-endian mode on the SysAD bus. The state of the ENDIAN signal at reset determines this
endian mode. However, there are important considerations when using the controller in a mixed-endian design. The
most important aspect of the endian issue is which byte lanes of the SysAD bus are activated for a particular address.
If the big-endian mode is implemented for the CPU interface, the controller swaps bytes within words and half-words
that are coming in and going out on the SysAD bus. All of the other interfaces of system controller operate in little-
endian mode.
The sections below view the endian issue from a programmer's perspective. They describe how to implement
mixed-endian designs and how to make code endian-independent.
Data in memory is always ordered in little-endian mode, even with a big-endian CPU.
Data in all internal registers and FIFOs is considered little endian regardless of CPU's endian mode.
Data addresses or Data byte order in the word are not swapped inside the device for accesses from a little-endian
V
4120A to all local registers and memory when "BIG" signal is Low.
R
Data addresses are swapped inside the device for accesses from a big-endian V
memory when "BIG" signal and "ENDCEN" signal are High.
Data byte order in the word are swapped inside the device for accesses from a big-endian CPU to all local registers
and memory when "BIG" signal is High and "ENDCEN" signal is Low.
3.7.2 Endian modes
The endian mode of a device refers to its word-addressing method and byte order:
Big-endian devices address data items at the big end (most significant bit number). The most-significant byte
(MSB) in an addressed data item is at the lowest address.
Little-endian devices address data items at the little end (least significant bit number). The most significant byte
(MSB) in an addressed data item is at the highest address.
The following figures indicate the bit and byte order of the two endian modes, as it applies to bytes within word-
sized data items. The bit order within bytes is the same for both modes. The big (most-significant) bit is on the left
side, and the little (least significant) bit is on the right side. Only the bit order of sub-items is reversed within a larger
addressable data item (half word, word, and double word) when crossing between the two endian modes. The sub-
items' order of significance within the larger data item remains the same. For example, the least significant half word
(LSHW) in a word is always to the right and the most significant half word (MSHW) is to the left.
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CHAPTER 3 SYSTEM CONTROLLER
Preliminary User's Manual S15543EJ1V0UM
4120A to all local registers and
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