NEC uPD98502 User Manual page 566

SWR
Operation:
vAddr ← ((offset
32 T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
if BigEndianMem = 1 then
pAddr ← pAddr
endif
byte ← vAddr
if (vAddr xor BigEndianCPU) = 0 then
2
data ← 0
else
data ← GPR [rt]
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
vAddr ← ((offset
64 T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
if BigEndianMem = 1 then
pAddr ← pAddr
endif
byte ← vAddr
if (vAddr xor BigEndianCPU) = 0 then
2
data ← 0
else
data ← GPR [rt]
endif
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
566
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Store Word Right (2/3)
16
) || offset ) + GPR [base]
15 15...0
|| (pAddr xor ReverseEndian
PSIZE - 1...3 2...0
2
|| 0
PSIZE - 1...2
2
xor BigEndianCPU
1...0
32
|| GPR [rt] || 0
31 – 8 * byte...0
8 * byte
|| 0
31 – 8 * byte
48
) || offset ) + GPR [base]
15 15...0
|| (pAddr xor ReverseEndian
PSIZE - 1...3 2...0
2
|| 0
PSIZE - 1...2
2
xor BigEndianCPU
1...0
32
|| GPR [rt] || 0
31 – 8 * byte...0
8 * byte
|| 0
31 – 8 * byte
Preliminary User's Manual S15543EJ1V0UM
3
)
8 * byte
32
|| 0
3
)
8 * byte
32
|| 0
SWR