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Core
Offset
SYSCNT
D8H
SYSCNT
DCH
SYSCNT
E0H
SYSCNT
E4H-FFH
SYSCNT
100H
SYSCNT
104H
SYSCNT
108H
SYSCNT
10CH
SYSCNT
110H
SYSCNT
114H
SYSCNT
118H
SYSCNT
11CH
SYSCNT
120H
SYSCNT
124H
SYSCNT
128H-FFFH
USB
00H
USB
04H
USB
08H
USB
0CH
USB
10H
USB
14H
USB
18H
USB
1CH
USB
20H
USB
24H
USB
28H
USB
2CH
USB
30H
USB
34H
USB
38H
USB
3CH
USB
40H
USB
44H
USB
48H
USB
4CH
USB
50H
USB
54H
USB
58H
USB
5CH
USB
60H
USB
64H
USB
68H
USB
6CH
USB
70H
USB
74H
USB
78H
USB
7CH
USB
80H
USB
84H
USB
88H
USB
8CH
USB
90H-FFH
Base address
ATM Cell Processor (ATM)
PCI Controller (PCI)
Ethernet Controller (Ether) #1 (n = 1)
Ethernet Controller (Ether) #2 (n = 2)
USB Controller (USB)
System Controller (SYSCNT)
52
CHAPTER 1 INTRODUCTION
Register
Name
Access by
Length
V
(Byte)
4
MACAR1
R
4
MACAR2
R
4
MACAR3
R
-
N/A
-
4
RMMDR
R/W
4
RMATR
R/W
4
SDMDR
R/W
4
SDTSR
R/W
4
SDPTR
R/W
4
SDRMR
R/W
4
SDRCR
R
4
SDRMR
R/W
4
SDRCR
R
4
MBCR
R/W
-
N/A
-
4
U_GMR
R/W
4
U_VER
R
-
N/A
-
-
N/A
-
4
U_GSR1
R
4
U_IMR1
R/W
4
U_GSR2
R
4
U_IMR2
R/W
4
U_EP0CR
R/W
4
U_EP1CR
R/W
4
U_EP2CR
R/W
4
U_EP3CR
R/W
4
U_EP4CR
R/W
4
U_EP5CR
R/W
4
U_EP6CR
R/W
-
N/A
-
4
U_CMR
R/W
4
U_CA
R/W
4
U_TEPSR
R
-
N/A
-
4
U_RP0IR
R/W
4
U_RP0AR
R
4
U_RP1IR
R/W
4
U_RP1AR
R
4
U_RP2IR
R/W
4
U_RP2AR
R
-
N/A
-
-
N/A
-
4
U_TMSA
R/W
4
U_TMBA
R/W
4
U_TMRA
R/W
4
U_TMWA
R
4
U_RMSA
R/W
4
U_RMBA
R/W
4
U_RMRA
R/W
4
U_RMWA
R
-
N/A
-
- 1001_0000H
- 1000_4000H
- 1000_2000H
- 1000_3000H
- 1000_1000H
- 1000_0000H
Preliminary User's Manual S15543EJ1V0UM
4120A
R
MAC Address Register 1
MAC Address Register 2
MAC Address Register 3
Reserved for future use
Boot ROM Mode Register
Boot ROM Access Timing Register
SDRAM Mode Register
SDRAM Type Selection Register
SDRAM Precharge Timing Register
SDRAM Precharge Mode Register
SDRAM Precharge Timer Count Register
SDRAM Refresh Mode Register
SDRAM Refresh Timer Count Register
Memory Bus Control Register
Reserved for future use
USB General Mode Register
USB Frame number/Version Register
Reserved for future use
Reserved for future use
USB General Status Register 1
USB Interrupt Mask Register 1
USB General Status Resister 2
USB Interrupt Mask Register 2
USB EP0 Control Register
USB EP1 Control Register
USB EP2 Control Register
USB EP3 Control Register
USB EP4 Control Register
USB EP5 Control Register
USB EP6 Control Register
Reserved for future use
USB Command Register
USB Command Address Register
USB Tx EndPoint Status Register
Reserved for future use
USB Rx Pool0 Information Register
USB Rx Pool0 Address Register
USB Rx Pool1 Information Register
USB Rx Pool1 Address Register
USB Rx Pool2 Information Register
USB Rx Pool2 Address Register
Reserved for future use
Reserved for future use
USB Tx MailBox Start Address Register
USB Tx MailBox Bottom Address Register
USB Tx MailBox Read Address Register
USB Tx MailBox Write Address Register
USB Rx MailBox Start Address Register
USB Rx MailBox Bottom Address Register
USB Rx MailBox Read Address Register
USB Rx MailBox Write Address Register
Reserved for future use
Description
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