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LWL
The contents of general register rt are internally bypassed within the processor so that no NOP is needed between
an immediately preceding load instruction which specifies register rt and a following LWL (or LWR) instruction
which also specifies register rt .
No address error exceptions due to alignment are possible.
Operation:
vAddr ← ((offset
32
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
if BigEndianMem = 0 then
pAddr ← pAddr
endif
byte ← vAddr
word ← vAddr
mem ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
temp ← mem
GPR [rt] ← temp
vAddr ← ((offset
64
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
if BigEndianMem = 0 then
pAddr ← pAddr
endif
byte ← vAddr
word ← vAddr
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
temp ← mem
GPR [rt] ← (temp
516
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Word Left (2/3)
16
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor ReverseEndian
PSIZE - 1...3
2...0
2
|| 0
PSIZE - 1...2
2
xor BigEndianCPU
1...0
xor BigEndianCPU
2
|| GPR [rt]
32 * word + 8 * byte + 7...32 * word
48
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor ReverseEndian
PSIZE - 1...3
2...0
2
|| 0
PSIZE - 1...2
2
xor BigEndianCPU
1...0
xor BigEndianCPU
2
|| GPR [rt]
32 * word + 8 * byte + 7...32 * word
32
|| temp
)
31
Preliminary User's Manual S15543EJ1V0UM
3
)
23 – 8 * byte...0
3
)
23 – 8 * byte...0
LWL
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