Page Mask Register; Cache Algorithm; Mask Values And Page Sizes - NEC uPD98502 User Manual

2.4.5.4 PageMask register (5)
The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison
mask that sets the page size for each TLB entry, as shown in Table 2-33. Page sizes must be from 1 Kbyte to 256
Kbytes.
TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets of
comparison are masked during address translation.
31
MASK : Page comparison mask, which determines the virtual page size for the corresponding entry.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
Table 2-33 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves
unexpectedly.
Page Size
1 Kbyte
4 Kbytes
16 Kbytes
64 Kbytes
256 Kbytes
CHAPTER 2 V
Table 2-32. Cache Algorithm
C Bit Value
0
1
2
3
4
5
6
7
Figure 2-37. Page Mask Register
19 18
0 MASK
13 8
Table 2-33. Mask Values and Page Sizes
18 17
0 0
0 0
0 0
0 0
1 1
Preliminary User's Manual S15543EJ1V0UM
4120A
R

Cache Algorithm

Cached
Cached
Uncached
Cached
Cached
Cached
Cached
Cached
11 10
0
11
Bit
16 15 14 13
0 0 0 0
0 0 0 0
0 0 1 1
1 1 1 1
1 1 1 1
0
12 11
0 0
1 1
1 1
1 1
1 1
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