Block Diagram Of Atm Cell Processor - NEC uPD98502 User Manual

4.1.2 Block diagram of ATM cell processor

V 4120A RISC
R
Processor
System
Controller
SDRAM
I/F
SDRAM
This block is an ATM cell processor. It consists of a 32-bit MCU, Peripherals (Interrupt Controller, Cell Timer,
Scheduling Table and Rx Lookup Table), DMA controllers, a Work-RAM, and SAR-Registers.
4.1.2.1 RISC core
This block is RISC micro-controller. Its features are as follows:
• High performance 32-bit RISC micro-controller, 76 MIPS @ 66 MHz
• 32 x 32-bit General Purpose Registers
• 32-bit ALU, 32-bit Shifter, 16 x 16 Multiply-Adder
• 1-KB Data RAM, 8-KB Instruction RAM, 8-KB Instruction Cache
4.1.2.2 Peripherals
• Interrupt Controller (INTC) and Interrupt Edge Detector (INTEDGE)
• Peripherals for ATM functions – Scheduling Table, Rx Lookup Table, and Cell Timer
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CHAPTER 4 ATM CELL PROCESSOR
Figure 4-1. Block Diagram of ATM Cell Processor
Ethernet
Controller
Controller
#1, #2
IBUS I/F
UTOPIA BUS
Controller
UTOPIA UTOPIA
Level2 MGR
Preliminary User's Manual S15543EJ1V0UM
USB
SAR Work
REGS RAM
Data
RAM
RISC Core
I cache
IRAM
ATM Cell Processor
IBUS
Peripherals