Information For Software; Nic Mode - NEC uPD98502 User Manual

7.6 Information for Software

7.6.1 NIC mode

7.6.1.1 Initialization
(1) Initialization by the V
R
The PCI Controller issues "retry" to all accesses from PCI-side until INITD bit in P_BCNT register is set to '1'.
Therefore, Initialization of the chip should be done before INITD bit is set to '1'.
The following sequence shows an example of initialization procedures required for the V
- Sets Subsystem Vendor ID register, Subsystem ID register, Min_Gnt register and Max_Lat register in
configuration space, if needed
- Sets '1' to "PME Clock" bit in PMC register, if PCI-clock does not be required to generate PME
- Sets base addresses to P_PLBA register and P_IBBA register
- Enables mask bits in P_IIMR register, if needed
- Sets data about power to P_PWCD register and P_PWDD register
- Sets commands the PCI Controller uses on Internal bus, I/O or memory, by ICMDS bit in P_BCNT
register
- Selects modes for data transfers by PDRTD bit, PPWRD bit, IDRTD bit, IPWRD bit in P_BCNT register.
- Sets '00' to PowerState field in PMCSR register in order to indicate that chip can be run.
- Sets a '1' to PMRDY bit in P_PPCR register to indicate that the issue for the transition of power state is
acceptable.
- Sets a '1' to INITD bit in P_BCNT register in order to indicate that the Initialization of the PCI Controller
has been completed.
(2) Initialization by PCI-Host
After the time INITD bit is set, the PCI Controller can accepts the access from PCI-side. An external PCI-Host
device is responsible to configure the configuration register of the PCI Controller so that the PCI Controller can run as
PCI-device.
The following sequence shows an example of initialization procedures required for external PCI-Host device.
- Sets a '1' to "Memory Access Enable" bit in command register
- Sets a '1' to "Bus Master Enable" bit in command register, if the chip executes transaction as PCI-master
- Sets a '1' to "Memory Write and Invalidate Enable" bit in command register, if needed
- Sets a '1' to "Parity Error Response" bit in command register, if needed
- Sets a '1' to "System Error Response " bit in command register, if needed
- Sets the cache line size of system to "Cache Line Size" register
- Sets "Latency Timer" register, if needed
- Sets base addresses to "Window Base Memory Address" register and "Register Base Memory Address"
register
CHAPTER 7 PCI CONTROLLER
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Preliminary User's Manual S15543EJ1V0UM
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