Beq Instruction Pipeline Activities (In Mips Iii Instruction Mode) - NEC uPD98502 User Manual

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2.3.4.3 Branch on equal instruction (BEQ rs, rt, offset)
IF stage
Same as the IF stage for the ADD instruction.
IT stage
Same as the IT stage for the ADD instruction.
During Φ 2, the register file is addressed with the rs and rt fields. A check is performed to
RF stage
determine if each corresponding bit position of these two operands has equal values. If they
are equal, the PC is set to PC + target, where target is the sign-extended offset field. If they are
not equal, the PC is set to PC + 4.
The next PC resulting from the branch comparison is valid at the beginning of Φ 2 for instruction
EX stage
fetch.
DC stage
This stage is a NOP for this instruction.
WB stage
This stage is a NOP for this instruction.
Figure 2-15. BEQ Instruction Pipeline Activities (In MIPS III Instruction Mode)
PClock
Phase
Cycle
90
CHAPTER 2 V
PCycle
Φ 1
Φ 2
Φ 1
Φ 2
IF1
IF2
RF1
RF2
IDC
ICA
ITLB
ITC
IDEC
RF
BAC
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Φ 1
Φ 2
Φ 1
Φ 2
EX1
EX2
DC1
DC2
EX
Φ 1
Φ 2
WB1
WB2

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