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Numbers (1) to (9) do not indicate the order in which USB Controller must perform processing. Instead, these
numbers correspond to those in the following explanation.
(1)
USB Controller is in the status where it waits to receive data (USB Packets) from the USB.
(2)
USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller
performs NRZI decoding, CRC check, and Bit Stuffing Error check.
(3)
USB Controller stores the received data into the FIFO.
(4)
USB Controller starts to fetch a new buffer descriptor.
(5)
USB Controller checks whether the fetched buffer descriptor is a link pointer or not.
(6)
If the fetched buffer descriptor is a link pointer, USB Controller updates the Pool Information Registers and
restarts to fetch a new buffer descriptor.
(7)
USB Controller then DMA-transfers data from the FIFO to system memory.
(8)
If USB Controller finds that the transferred data is the last data, renews the Size field and Last bit of Buffer
Descriptor and writes the Rx indication into the prepared Mailbox.
(9)
USB Controller updates the write pointer of the MailBox (Rx MailBox Write Address Register Address:
1000_108CH). Also, it sets the receive completion bit of the USB General Status Register 1 and issues an
interrupt to the V
CHAPTER 6 USB CONTROLLER
4120A if it is not masked.
R
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