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DMULTU
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
DMULTU rs, rt
Description:
The contents of general register rs and the contents of general register rt are multiplied, treating both operands as
unsigned values. No overflow exception occurs under any circumstances.
When the operation completes, the low-order word of the double result is loaded into special register LO , and the
high-order word of the double result is loaded into special register HI .
If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct
operation requires separating reads of HI or LO from writes by a minimum of two instructions.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
← undefined
64
T-2:
LO
← undefined
HI
← undefined
T-1:
LO
← undefined
HI
← (0 || GPR [rs])
T:
t
← t
LO
63..0
← t
HI
127..64
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Doubleword Multiply Unsigned
21 20
16 15
rs
rt
5
5
(0 || GPR [rt])
*
Preliminary User's Manual S15543EJ1V0UM
0
0 0 0 0 0 0 0 0 0 0
10
DMULTU
6 5
0
DMULTU
0 1 1 1 0 1
6
483
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