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1.7.4 System control interface
Pin Name
Pin No.
SCLK
V1
CLKSL
U1
PSMD
AA3
PSTBY
AA2
PUMD
B27
PUSTBY
D25
BIG
D16
ENDCEN
C15
EXINT_B
A15
EXNM_BI
A13
RSTB_B
AB30
RMSL0
E11
RMSL1
B11
38
CHAPTER 1 INTRODUCTION
I/O
Active Level
I
System clock (33 MHz)
I
Clock select (100 MHz/66 MHz)
I
System PLL mode control (0: normal, 1: through)
I
System PLL standby mode control (0: active, 1: standby)
I
USB PLL mode control (0: normal, 1: through)
I
USB PLL standby mode control (0: active, 1: standby)
I
H
V
4120 big endian mode
R
I
Endian conversion enable
I
L
External interrupt
I
L
External non-maskable interrupt
I
L
System reset
I
ROM access bus width select
I
(RMSL1/0 = L/L: 32-bit, L/H: 16-bit, H/L: 8-bit)
Preliminary User's Manual S15543EJ1V0UM
Function
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