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BNEL
31
26 25
BNEL
0 1 0 1 0 1
6
Format:
BNEL rs, rt, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset, shifted left two bits and sign-extended. The contents of general register rs and the contents of general
register rt are compared. If the two registers are not equal, then the program branches to the target address, with
a delay of one instruction.
If the conditional branch is not taken, the instruction in the branch delay slot is nullified.
Operation:
target ← (offset
32
T:
condition ← (GPR [rs] ≠ GPR [rt])
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
target ← (offset
64
T:
condition ← (GPR [rs] ≠ GPR [rt])
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Branch On Not Equal Likely
21 20
16 15
rs
rt
5
5
14
2
)
|| offset || 0
15
46
2
)
|| offset || 0
15
Preliminary User's Manual S15543EJ1V0UM
BNEL
offset
16
0
463
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