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SLLV
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
SLLV rd, rt, rs
Description:
The contents of general register rt are shifted left the number of bits specified by the low-order five bits contained in
general register rs , inserting zeros into the low-order bits.
The result is placed in register rd .
In 64-bit mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for all
shift amounts, including zero; SLLV with zero shift amount truncates a 64-bit value to 32 bits and then sign extends
this 32-bit value. SLLV, unlike nearly all other word operations, does not require an operand to be a properly sign-
extended word value to produce a valid sign-extended word result.
Operation:
s ← GPR [rs]
32
T:
GPR [rd] ← GPR [rt]
s ← 0 || GPR [rs]
64
T:
temp ← GPR [rt]
GPR [rd] ← (temp
Exceptions:
None
Caution SLLV with a shift amount of zero may be treated as a NOP by some assemblers, at some
optimization levels. If using SLLV with a purpose of sign-extension, check the assembler
specification.
548
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Shift Left Logical Variable
21 20
16 15
rs
rt
5
5
4...0
s
|| 0
(31 - s)...0
4...0
s
|| 0
(31 - s)...0
32
)
|| temp
31
Preliminary User's Manual S15543EJ1V0UM
11 10
6 5
0
rd
0 0 0 0 0
5
5
SLLV
0
SLLV
0 0 0 1 0 0
6
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