Instruction Cache Line Format; Data Cache Line Format - NEC uPD98502 User Manual

22 21
V
1
PTag : Physical tag (bits 31 to 10 of physical address)
V : Valid bit
Data : Cache data
2.7.2.2 Organization of the data cache (D-cache)
Each line of D-cache data has an associated 25-bit tag that contains a 22-bit physical address, a Valid bit, a Dirty
bit, and a Write-back bit.
The V 4120A Core D-cache has the following characteristics :
R
write-back
direct-mapped
indexed with a virtual address
checked with a physical tag
organized with a 4-word (16-byte) cache line.
Figure 2-68 shows the format of a 4-word (16-byte) D-cache line.
24 23
W V
1 1
W : Write-back bit (set if cache line has been written)
D : Dirty bit
V : Valid bit
PTag : Physical tag (bits 31 to 10 of physical address)
Data : D-cache data
170
CHAPTER 2 V
Figure 2-67. Instruction Cache Line Format
PTag
22
Figure 2-68. Data Cache Line Format
21
22
D
1
Preliminary User's Manual S15543EJ1V0UM
4120A
R
31
Data
Data
Data
Data
PTag
22
63
Data
Data
0
0
0
0