NEC uPD98502 User Manual page 496

HIBERNATE
31 26 25 24
COP0
CO
0 1 0 0 0 0
1
6 1
Format:
HIBERNATE
Description:
HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode.
When the HIBERNATE instruction finishes the WB stage, the processor wait by the SysAD bus is idle state, after
then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline.
Cold Reset causes the Hibernate mode to the Fullspeed mode transition.
Operation:
32, 64 T:
T+1: Hibernate operation ()
Exceptions:
Coprocessor unusable exception
496
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Hibernate
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Preliminary User's Manual S15543EJ1V0UM
0
19
HIBERNATE
6 5 0
HIBERNATE
1 0 0 0 1 1
6