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DSLLV
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
DSLLV rd, rt, rs
Description:
The contents of general register rt are shifted left by the number of bits specified by the low-order six bits contained
in general register rs , inserting zeros into the low-order bits. The result is placed in register rd .
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
s ← GPR [rs]
64
T:
GPR [rd] ← GPR [rt]
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Doubleword Shift Left Logical Variable
21 20
rs
rt
5
5
5..0
s
|| 0
(63 - s)..0
Preliminary User's Manual S15543EJ1V0UM
16 15
11 10
rd
0 0 0 0 0
5
DSLLV
6 5
0
DSLLV
0 1 0 1 0 0
5
6
0
485
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