Delayed Read Transaction From Internal Bus To Pci - NEC uPD98502 User Manual

7.2.1.4 Read issue from internal bus to PCI
(1) Delayed read transaction
When IDRTD bit in P_BCNT register is '0', the PCI Controller uses "Delayed Read Transaction" rule for read
transactions from internal bus-side to PCI-side. The rule is as follows;
<1> An internal bus block connecting to the internal bus issues the read transaction to an external PCI target
device.
<2> The PCI Controller responds to this access and issues "retry" to internal bus block. However, the PCI
Controller latches the address and the command, and stores the access issued. Then, the PCI Controller
issues "retry" to all the access until the transaction corresponding to the latched command on PCI bus has
been completed.
<3> The PCI Controller issues the read transaction to PCI target device.
<4> The PCI target device accepts the access. The read data from the PCI target device is stored in the internal
FIFO.
<5> The PCI Controller waits that the same access with that is issued comes on the internal bus. The PCI
Controller issues "retry" to other accesses.
<6> When the same access comes, which means the access with the same address and the same command,
the PCI Controller accepts this access and returns the data from the internal FIFO.
Figure 7-4. Delayed Read Transaction from Internal Bus to PCI
The maximum burst size is 16 words so that when more than 16 words read burst is issued on Internal bus, the
PCI Controller issues "disconnect" at 16th word. In the case of a burst access across the address boundary, it issues
"disconnect", too.
When the same read access that has been issued does not come within 2
data in the internal FIFO, sets PFDSC bit of P_PGSR register and reports to PCI-Host by interrupt (if not masked).
Then, the PCI Controller can accept the new read transaction from Internal bus, again.
When the PCI Controller receives target abort/master abort on PCI bus after it has accepted delayed-read from
PCI-side, it sets RTABT/RMABT bit of P_IGSR register and RDTAT/RDMAT bit of P_PGSR register, and reports by
interrupts to an external PCI-Host device and the V
words to internal bus block.
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CHAPTER 7 PCI CONTROLLER
<4>
PCI
Target
Controller
Device
<3>
4120A (if not masked). Then, the PCI Controller returns all "0"
R
Preliminary User's Manual S15543EJ1V0UM
<6>
PCI Internal
<5>
Bus Block
<2>
<1>
15 clocks, the PCI Controller discards the