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TLBR
31
26 25
COP0
CO
0 1 0 0 0 0
1
6
1
Format:
TLBR
Description:
The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the
TLB Index register.
The G bit (which controls ASID matching) read from the TLB is written into both of the EntryLo0 and EntryLo1
registers. The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are
greater than the number of TLB entries in the processor.
Operation:
PageMask ← TLB [Index
32
T:
EntryHi ← TLB [Index
EntryLo1 ← TLB [Index
EntryLo0 ← TLB [Index
PageMask ← TLB [Index
64
T:
EntryHi ← TLB [Index
EntryLo1 ← TLB [Index
EntryLo0 ← TLB [Index
Exceptions:
Coprocessor unusable exception
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Read Indexed TLB Entry
24
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
]
5...0
127...96
]
and not TLB [Index
5...0
95...64
]
|| TLB [Index
5...0
63...33
]
|| TLB [Index
5...0
31...1
]
5...0
255...192
]
and not TLB [Index
5...0
191...128
]
|| TLB [Index
5...0
127...65
]
|| TLB [Index
5...0
63...1
Preliminary User's Manual S15543EJ1V0UM
0
19
]
5...0
127...96
]
5...0
76
]
5...0
76
]
5...0
255...192
]
5...0
140
]
5...0
140
TLBR
6 5
0
TLBR
0 0 0 0 0 1
6
577
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