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32-bit mode
FFFF_ FFFFH
0.5 Gbytes with
TLB mapping
E000_ 0000H
DFFF_ FFFFH
0.5 Gbytes with
TLB mapping
C000_ 0000H
BFFF_FFFFH
0.5 Gbytes without
TLB mapping
uncacheable
A000_ 0000H
9FFF_FFFFH
0.5 Gbytes without
TLB mapping
cacheable
8000_ 0000H
7FFF_FFFFH
2 Gbytes with TLB
mapping
0000_0000H
Notes 1.
The V
4120A uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to
R
bits 32 to 63, and the resulting 32 bits are used for addressing. Usually, a 64-bit instruction is used for
the program in 32-bit mode.
2.
The K0 field of the Config register controls cacheability of kseg0 and ckseg0.
CHAPTER 2 V
Figure 2-30. Kernel Mode Address Space
Note 1
FFFF_ FFFF_ FFFF_ FFFFH
kseg3
FFFF_ FFFF_ E000_ 0000H
FFFF_ FFFF_ DFFF_ FFFFH
FFFF_ FFFF_ C000_ 0000H
ksseg
FFFF_ FFFF_ BFFF_ FFFFH
FFFF_ FFFF_ A000_ 0000H
FFFF_ FFFF_ 9FFF_ FFFFH
kseg1
FFFF_ FFFF_ 8000_ 0000H
FFFF_ FFFF_ 7FFF_ FFFFH
kseg0
C000_ 00FF_ 8000_ 0000H
C000_ 00FF_ 7FFF_ FFFFH
C000_ 0000_ 0000_ 0000H
BFFF_ FFFF_ FFFF_ FFFFH
8000_ 0000_ 0000_ 0000H
7FFF_ FFFF_ FFFF_ FFFFH
4000_ 0100_ 0000_ 0000H
4000_ 00FF_ FFFF_ FFFFH
kuseg
4000_ 0000_ 0000_ 0000H
3FFF_ FFFF_ FFFF_ FFFFH
0000_ 0100_ 0000_ 0000H
0000_ 00FF_ FFFF_ FFFFH
0000_ 0000_ 0000_ 0000H
Preliminary User's Manual S15543EJ1V0UM
4120A
R
64-bit mode
0.5 Gbytes with
TLB mapping
0.5 Gbytes with
TLB mapping
0.5 Gbytes without
TLB mapping
uncacheable
0.5 Gbytes without
TLB mapping
cacheable
Address error
With TLB mapping
Without TLB mapping
Address error
1 Tbyte with TLB
mapping
Address error
1 Tbyte with TLB
mapping
ckseg
cksseg
ckseg1
ckseg0
Note 2
xkseg
xkphys
xksseg
xkuseg
111
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