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BGTZL
31
26 25
BGTZL
0 1 0 1 1 1
6
Format:
BGTZL rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset , shifted left two bits and sign-extended. The contents of general register rs are compared to zero. If the
contents of general register rs are greater than zero, then the program branches to the target address, with a delay
of one instruction. If the conditional branch is not taken, the instruction in the branch delay slot is nullified.
Operation:
target ← (offset
32
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
target ← (offset
64
T:
condition ← (GPR [rs]
T+1: if condition then
PC ← PC + target
else
NullifyCurrentInstruction
endif
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Branch On Greater Than Zero Likely
21 20
16 15
0
rs
0 0 0 0 0
5
5
14
2
)
|| offset || 0
15
= 0) and (GPR [rs] ≠ 0
31
46
2
)
|| offset || 0
15
= 0) and (GPR [rs] ≠ 0
63
Preliminary User's Manual S15543EJ1V0UM
offset
16
32
)
64
)
BGTZL
0
455
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