NEC uPD98502 User Manual page 405

7.5.19.5 Status register
This register is used to show PCI bus related events status. These bits are set when events related to the status on
PCI bus and reset to '0' by writing '1'.
In Host-mode, any bit in this register is not set even if corresponding events occur.
Bits Field
15 Detected Parity
Error
14 Signaled
System Error
13 Received
Master Abort
12 Received
Target Abort
11 Signaled Target
Abort
10:9 DEVSEL_B
timing
8 Master Data
Parity Error
7 Fast Back-to-
Back Capable
6 Reserved
5 66 MHz Enable
4 Capabilities List
3:0 Reserved
CHAPTER 7 PCI CONTROLLER
R/W Default
Internal PCI
bus
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R R 01
R/W R/W 0
R R 0
R R 0
R R 0
R R 1
R R 0
Preliminary User's Manual S15543EJ1V0UM
Description
This bit is set to a '1' when the PCI Controller detects a parity
error.
This bit is set to a '1' when the PCI Controller asserts SERR_B.
This bit is set to a '1' when the PCI Controller terminates its
transaction with Master-Abort as master device.
This bit is set to a '1' when the PCI Controller receives Target-
Abort and its transaction is terminated as master device.
This bit is set to a '1' when the PCI Controller terminates a
transaction with Target-Abort as target device.
Hardwired to '01', because the PCI Controller asserts DEVSEL_B
at medium speed.
This bit is set when three conditions as the follows are met:
(1) The bus agent asserted PERR_B itself (on a read) or
observed PERR_B asserted (on a write)
(2) The agent setting the bit acted as the bus master for the
operation in which the error occurred
(3) The Parity Error Response bit is set to a '1'
Hardwired to a '0', because the PCI Controller does not accept
fast back-to-back transactions when the transactions to the
different agents are required.
Hardwired to a '0'.
Hardwired to a '0', because the PCI Controller can be used at
33 MHz only.
Hardwired to a '1', because the PCI Controller has the PPMI
function as New Capability.
Hardwired to '0's.
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