NEC uPD98502 User Manual page 22

Table No.
3-1 Endian Configuration Table..........................................................................................................................202
3-2 Endian Translation Table in Endian Converter.............................................................................................202
3-3 External Pin Mapping...................................................................................................................................205
3-4 Examples of Memory Performance (4-word-burst access from CPU)..........................................................206
3-5 Examples of Memory Performance (4-word-burst access from IBUS Master) .............................................206
3-6 Boot-ROM Size Configuration at Reset .......................................................................................................213
3-7 Command Sequence ...................................................................................................................................214
3-8 SDRAM Size Configuration at Reset ...........................................................................................................216
3-9 SDRAM Configurations Supported ..............................................................................................................216
3-10 SDRAM Word Order for Instruction-Cache Line-Fill.....................................................................................217
3-11 Endian Translation Table for the data swap mode (IBUS master) ...............................................................221
3-12 Endian Translation Table for the data swap mode (IBUS slave)..................................................................222
4-1 List of Tx Packet Attribute ............................................................................................................................249
4-2 List of Rx Pool Attributes..............................................................................................................................253
4-3 Commands...................................................................................................................................................257
4-4 Reception Errors That Can Occur During Packet Reception .......................................................................275
4-5 Error Reporting Priorities..............................................................................................................................275
5-1 Ethernet Controller's Register Categories....................................................................................................279
5-2 MAC Control Register Map ..........................................................................................................................279
5-3 Statistics Counter Register Map...................................................................................................................281
5-4 DMA and FIFO Management Registers Map ...............................................................................................283
5-5 Interrupt and Configuration Registers Map ..................................................................................................284
5-6 Attribute for Transmit Descriptor ..................................................................................................................301
5-7 Attribute for Receive Descriptor ...................................................................................................................302
7-1 Device Number Decode Table .....................................................................................................................387
8-1 Correspondence between Baud Rates and Divisors....................................................................................417
10-1 EEPROM Initial Data ...................................................................................................................................428
10-2 EEPROM Command List .............................................................................................................................428
A-1 CPU Instruction Operation Notations ...........................................................................................................432
A-2 Load and Store Common Functions ............................................................................................................433
A-3 Access Type Specifications for Loads/Stores ..............................................................................................434
B-1 V 4120A CPU Coprocessor 0 Hazards .......................................................................................................591
R
B-2 Calculation Example of CP0 Hazard and Number of Instructions Inserted ..................................................594
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LIST OF TABLES (2/2)
Title
Preliminary User's Manual S15543EJ1V0UM
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