Table of Contents
Advertisement
Numbers (1) to (12) do not indicate the order in which USB Controller must perform processing. Instead, these
numbers correspond to those in the following explanation.
(1)
USB Controller is in the status where it waits to receive data (USB Packets) from the USB.
(2)
USB Controller receives data (USB Packets) from the USB. As it is receiving the data, USB Controller
performs NRZI decoding, CRC check, and Bit Stuffing Error check.
(3)
USB Controller stores the received data into the FIFO.
(4)
USB Controller checks whether there is buffer remaining in system memory area or not (checks if USB
Controller should fetch new buffer descriptor or not).
(5)
If the buffer is not remaining in system memory area, USB Controller starts to fetch new buffer descriptor.
(6)
USB Controller checks whether the fetched buffer descriptor is a link pointer or not.
(7)
If the fetched buffer descriptor is a link pointer, USB Controller updates the Pool Information Registers and
restarts to fetch a new buffer descriptor.
(8)
USB Controller then DMA-transfers data from the FIFO to system memory.
(9)
USB Controller checks whether the DMA-transferred data is less than Max Packet Size.
(10) USB Controller checks whether buffer area becomes full or not.
(11) USB Controller updates the Size field and Last bit of Buffer Descriptor and writes the Rx indication into the
prepared Mailbox.
(12) USB Controller updates the write pointer of the MailBox (Rx MailBox Write Address Register Address:
1000_108CH). Also, it sets the receive completion bit of the USB General Status Register 1 and issues an
interrupt to the V
CHAPTER 6 USB CONTROLLER
4120A if it is not masked.
R
Preliminary User's Manual S15543EJ1V0UM
357
Advertisement
Table of Contents
