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ADDI
31
26 25
ADDI
0 0 1 0 0 0
6
Format:
ADDI rt, rs, immediate
Description:
The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The
result is placed into general register rt. In 64-bit mode, the operand must be valid sign-extended, 32-bit values.
An overflow exception occurs if carries out of bits 30 and 31 differ (2's complement overflow). The destination
register rt is not modified when an integer overflow exception occurs.
Operation:
GPR [ rt] ← GPR [ rs] + (immediate
32
T:
temp ← GPR [ rs] + (immediate
64
T:
GPR [ rt] ← (temp
Exceptions:
Integer overflow exception
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Add Immediate
21 20
16 15
rs
rt
5
5
16
)
|| immediate
15
48
)
|| immediate
15
32
)
|| temp
31
31...0
Preliminary User's Manual S15543EJ1V0UM
immediate
16
15...0
15...0
ADDI
0
437
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