Host Mode - NEC uPD98502 User Manual

- Sets a '1' to PME_En bit in PMCSR register, if needed
Then, the PCI-Host device initializes internal registers.
- Sets the value of base address in P_IBBA register, if needed
- Enables mask bits in P_PIMR register, if needed
- Sets Retry Timer register, if needed
(3) Error
In the case that Error described in 7.2.3 Abnormal Termination occurs, the PCI Controller sets bits in Status
register of configuration space, P_IGSR register and P_PGSR register, and issues interrupts to the V
external PCI-Host device (if not masked). The V
handle these error statuses. The PCI Controller would stop the current transaction, and returns to the state in which
the PCI Controller can accept new accesses.
(4) Software Reset
When PCI-Host writes to P_SWRR register for Software Reset, the PCI Controller sets SRREQ bit in P_IGSR
register and reports to the V
sequence.
The V 4120A should assert warm-reset signals or cold-reset signals for each blocks inside chip, if it wants to reset
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the chip.
(5) Transition of Power State
When PCI-Host writes to PowerState field in PMCSR register to change the power state of the chip, the PCI
Controller resets PMRDY bit in P_PPCR register, sets PPREQ bit in P_IGSR register and reports to the V
interrupt (if not masked). What transition is required is indicated by PMRQ0 bit, PMRQ1 bit and PMRQ3 bit in PMCSR
register.
However, the PCI Controller does not change the power state of the chip. The V
the transition of the power state.
If the V 4120A wants the transition of power state, it can generate PME_B by writing '1' to PMERQ bit in P_PPCR
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register.

7.6.2 Host mode

In Host mode, the host on PCI bus is the PCI Controller itself. This means that the V
initialization.
7.6.2.1 Initialization
In Host mode, the host on PCI bus is the PCI Controller itself. This means that the V
initialization.
The PCI Controller issues "retry" to all accesses from PCI-side until INITD bit in P_BCNT register is set to '1'.
The following sequence shows an example of configuration register initialization.
- Sets Subsystem Vendor ID register, Subsystem ID register, Min_Gnt register and Max_Lat register in
configuration space
- Sets a '1' to "Memory Access Enable" bit in command register
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CHAPTER 7 PCI CONTROLLER
4120A and the external PCI-Host device are responsible for how to
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4120A by interrupt (if not masked). But the PCI Controller does not reset itself by this
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Preliminary User's Manual S15543EJ1V0UM
4120A and an
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4120A by
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4120A should be responsible for
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4120A is responsible for
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4120A is responsible for
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