En_Rxfcr (Receive Fifo Control Register); En_Rxdpr (Receive Descriptor Pointer); Rx Fifo Control Mechanism - NEC uPD98502 User Manual

5.2.30 En_RXFCR (Receive FIFO Control Register)

Bits Field
31:26 UWM
[7:2]
25:24 Reserved
23:18 LWN
[7:2]
17:8 Reserved
7:2 RX_DRTH
1:0 Reserved
To internal bus
Request
to transmit
data
Request
to transmit
EOF
data

5.2.31 En_RXDPR (Receive Descriptor Pointer)

Bits Field
31:2 RCVDP
1:0 Reserved
CHAPTER 5 ETHERNET CONTROLLER
R/W Default
R/W 30H Upper Water Mark:
This pointer is used with Auto Flow Control Enable bit in En_TXCR. When
the receiving data fill level exceeds this pointer, the transmit module
generates a flow control frame automatically.
R/W 0 Reserved for future use. Write 0s.
R/W 10H Lower Water Mark:
R/W 0 Reserved for future use. Write 0s.
R/W 10H Receive Drain Threshold Level
This threshold is enable to the transmit data to the IBUS via internal DMAC
form the FIFO. Please see the Figure 5-3. This pointer is a word pointer.
R/W 0 Reserved for future use. Write 0s.
Figure 5-3. Rx FIFO Control Mechanism
Rx_FIFO (256 Bytes)
DRTH
DRTH
DRTH
DRTH
R/W Default
R/W 0 Receive Descriptor Pointer:
Please see the Section 5.3.5.
R/W 0 Reserved for future use. Write 0s.
Preliminary User's Manual S15543EJ1V0UM
Description
From MAC Control Block
No Packet
data
Beginning
of the
frame
Receiving
frame
Received
End of frame
Description
297