Table of Contents
Advertisement
LHU
31
26 25
LHU
1 0 0 1 0 1
6
Format:
LHU rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the halfword at the memory location specified by the effective address are zero-extended and
loaded into general register rt .
If the least-significant bit of the effective address is non-zero, an address error exception occurs.
Operation:
vAddr ← ((offset
32
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
GPR [rt] ← 0
vAddr ← ((offset
64
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr
GPR [rt] ← 0
Exceptions:
TLB refill exception
TLB invalid exception
Bus Error exception
Address error exception
512
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Halfword Unsigned
21 20
base
rt
5
5
16
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian
PSIZE - 1...3
2...0
2
xor (BigEndianCPU
|| 0)
2...0
16
|| mem
15 + 8 * byte...8 * byte
48
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian
PSIZE - 1...3
2...0
2
xor (BigEndianCPU
|| 0)
2...0
48
|| mem
15 + 8 * byte...8 * byte
Preliminary User's Manual S15543EJ1V0UM
16 15
2
|| 0))
2
|| 0))
LHU
offset
16
0
Advertisement
Table of Contents
