Virtual Address Space; Virtual-To-Physical Address Translation - NEC uPD98502 User Manual

2.4.2 Virtual address space

This section describes the virtual/physical address space and the manner in which virtual addresses are converted
or "translated" into physical addresses in the TLB. The V
depending on whether the processor is operating in 32-bit or 64-bit mode.
In 32-bit mode, addresses are 32 bits wide. The maximum user process size is 2 Gbytes (2
In 64-bit mode, addresses are 64 bits wide. The maximum user process size is 1 Tbyte (2
As shown in Figure 2-25, the virtual address is extended with an address space identifier (ASID), which reduces
the frequency of TLB flushing when switching contexts. This 8-bit ASID is in the CP0 EntryHi register, described later
in this chapter. The Global (G) bit is in the EntryLo0 and EntryLo1 registers, described later in this section.
1 The virtual page number (VPN) in the
virtual address (VA) is compared with
the VPN in the TLB.
2 If there is a match, the page frame
number (PFN) representing the high-
order bits of the physical address is
output from the TLB.
3 The offset is then added to the PFN
passing through the TLB.
102
CHAPTER 2 V
Figure 2-25. Virtual-to-Physical Address Translation
G
TLB
Preliminary User's Manual S15543EJ1V0UM
4120A
R
4120A virtual address can be either 32 or 64 bits wide,
R
Virtual address
ASID VPN
ASID VPN
PFN
PFN
Physical address
31
).
40
).
Offset
TLB
entry
Offset