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LWU
31
26 25
LWU
1 0 1 1 1 1
6
Format:
LWU rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the word at the memory location specified by the effective address are loaded into general register
rt . The loaded word is zero-extended.
If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
vAddr ← ((offset
32
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr
GPR [rt] ← 0
vAddr ← ((offset
64
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr
GPR [rt] ← 0
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Word Unsigned
21 20
base
rt
5
5
16
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian || 0
PSIZE - 1...3
2...0
xor (BigEndianCPU || 0
2...0
32
|| mem
31 + 8 * byte...8 * byte
48
)
|| offset
) + GPR [base]
15
15...0
|| (pAddr
xor (ReverseEndian || 0
PSIZE - 1...3
2...0
xor (BigEndianCPU || 0
2...0
32
|| mem
31 + 8 * byte...8 * byte
Preliminary User's Manual S15543EJ1V0UM
16 15
2
))
2
)
2
))
2
)
LWU
offset
16
0
521
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