System Control Coprocessor (Cp0) Instructions (2/2) - NEC uPD98502 User Manual

Table 2-21. System Control Coprocessor (CP0) Instructions (2/2)
Instruction
Read Indexed TLB TLBR
Entry The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page
mask register.
Write Indexed TLB TLBWI
Entry
The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry
indexed by the index register.
Write Random TLB TLBWR
Entry The contents of the entryHi, entryLo0, entryLo1, or page mask register are loaded into the TLB entry
indexed by the random register.
Probe TLB For TLBP
Matching Entry The address of the TLB entry that matches with the contents of entryHi register is loaded into the index
register.
Return From Exception ERET
The program returns from exception, interrupt, or error trap.
Instruction
STANDBY STANDBY
The processor's operating mode is transited from fullspeed mode to standby mode.
SUSPEND SUSPEND
The processor's operating mode is transited from fullspeed mode to suspend mode.
HIBERNATE HIBERNATE
The processor's operating mode is transited from fullspeed mode to hibernate mode.
Instruction
Cache Operation Cache op, offset (base)
The 16-bit offset is sign extended to 32 bits and added to the contents of the register case, to form
virtual address. This virtual address is translated to physical address with TLB. For this physical
address, cache operation that is indicated by 5-bit sub-opcode is performed.
CHAPTER 2 V
Format and Description
Format and Description
Format and Description
Preliminary User's Manual S15543EJ1V0UM
4120A
R
COP0 CO
COP0 CO
base
op
CACHE
funct
funct
offset
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