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DSUBU
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
DSUBU rd, rs, rt
Description:
The contents of general register rt are subtracted from the contents of general register rs to form a result. The
result is placed into general register rd .
The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow. No
integer overflow exception occurs under any circumstances.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
GPR [rd] ← GPR [rs] − GPR [rt]
64
T:
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)
494
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Doubleword Subtract Unsigned
21 20
16 15
rs
rt
5
5
Preliminary User's Manual S15543EJ1V0UM
11 10
6 5
0
rd
0 0 0 0 0
5
5
DSUBU
0
DSUBU
1 0 1 1 1 1
6
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