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5.1 Overview
This section describes Ethernet Controller block. This Ethernet Controller block comprises of a 10/100 Mbps
Ethernet MAC (Media Access Control), data transmit/receive FIFOs, DMA and internal bus interface.
The µ PD98502 implements 2-channel Ethernet Controller.
5.1.1 Features
• IEEE802.3/802.3u/802.3x Compliant:
- 10/100 Mbps Ethernet MAC
- Media Independent Interface (MII)
- Flow Control
• Full duplex operation for 10 Mbps and 100 Mbps
• Address Filtering:
- unicast
- multicast
- broadcast
• Statistics counters for management information
- RMON
- SNMP MIB
• Large independent receive and transmit FIFOs
• Direct Memory Access (DMA) with programmable burst size providing for low CPU utilization
• Internal Bus interface (IBUS): 32 bits @66 MHz
5.1.2 Block diagram of Ethernet controller block
The following list describes this block's hardware components, and Figure 5-1 shows a block diagram of this block:
IBUS Interface
DMA Controller
FIFO Controller
MAC Core
MII I/O Buffer
CHAPTER 5 ETHERNET CONTROLLER
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Data transfer is done through this IBUS interface between CPU and Ethernet
Controller or memory and Ethernet Controller. This performance is approximately
2 Gbps (32 bits x 66 MHz). Also in this block, IBUS protocol operation is done
[retry, disconnect and so on].
-
DMA controller contains dual reception and transmission controller, which handle
data transfers between memory and FIFOs. This DMA controller supports a byte
alignment.
-
FIFO controller contains two independent FIFOs for reception and transmission.
This controller supports automatic packet deletion on reception (after a collision or
address filtering) and packet retransmission after a collision on transmission.
-
MAC Core is fully compliant with IEEE802.3, IEEE802.3u and IEEE802.3x.
-
MII I/O buffers are compliant IEEE802.3u and are connect to standard PHY
device.
Preliminary User's Manual S15543EJ1V0UM
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