Uartlsr (Uart Line Status Register) - NEC uPD98502 User Manual

8.3.11 UARTLSR (UART Line Status Register)

This register reports the current state of the transmitter and receiver logic.
Bits Field
31:8 Reserved
7 RFERR
6 TEMT
5 THRE
4 BI
3 FE
2 PE
1 OE
0 DR
422
CHAPTER 8 UART
R/W Default
R/W 0 Hardwired to 0.
R/W 0 Receiver FIFO Error.
1 = parity, framing, or break error in receiver buffer.
0 = no such error.
R/W 1 Transmitter Empty.
1 = transmitter holding and shift registers empty.
0 = transmitter holding or shift register not empty.
R/W 1 Transmitter Holding Register Empty.
1 = transmitter holding register empty.
0 = transmitter holding register not empty.
Transmit data is stored in the UART Transmitter Data
Holding Register (UARTTHR)
R/W 0 Break Interrupt.
1 = break received on URSDI signal.
0 = no break.
R/W 0 Receive-Data Framing Error.
1 = framing error on receive data.
0 = no such error.
R/W 0 Receive-Data Parity Error.
1 = parity error on receive data.
0 = no such error.
R/W 0 Receive-Data Overrun Error.
1 = overrun error on receive data.
0 = no such error.
R/W 0 Receive-Data Ready.
1 = receive data buffer full.
0 = receive data buffer not full.
Receive data is stored in the UART Receiver Data Buffer Register
(UARTRBR).
Preliminary User's Manual S15543EJ1V0UM
Description