Registers; Register Map; Ethernet Controller's Register Categories; Mac Control Register Map - NEC uPD98502 User Manual

5.2 Registers

Registers of this block are categorized following four categories as shown in Table 5-1.
V 4120A controls following registers.
R
The µ PD98502 has 2-channel Ethernet Controller, #1 controller's base address is 1000_2000H, #2 controller's
base address is 1000_3000H.
1000_2000H:1000_213FH (Ethernet Controller #1),
1000_3000H:1000_313FH (Ethernet Controller #2)
1000_2140H:1000_21FFH (Ethernet Controller #1),
1000_3140H:1000_31FFH (Ethernet Controller #2)
1000_2200H:1000_2233H (Ethernet Controller #1),
1000_3200H:1000_3233H (Ethernet Controller #2)
1000_2234H:1000_223FH (Ethernet Controller #1),
1000_3234H:1000_323FH (Ethernet Controller #2)

5.2.1 Register map

5.2.1.1 MAC control registers
MAC Control Registers' map is shown in Table 5-2.
Offset Address Register Name
1000_m000H En_MACC1
1000_m004H En_MACC2
1000_m008H En_IPGT
1000_m00CH En_IPGR
1000_m010H En_CLRT
1000_m014H En_LMAX
1000_m018H: N/A
1000_m01CH
1000_m020H En_RETX
1000_m024H: N/A
1000_m050H
1000_m054H En_LSA2
1000_m058H En_LSA1
1000_m05CH En_PTVR
1000_m060H N/A
1000_m064H En_VLTP
1000_m080H En_MIIC
1000_m084H: N/A
1000_m090H
1000_m094H En_MCMD
1000_m098H En_MADR
1000_m09CH En_MWTD
1000_m0A0H En_MRDD
1000_m0A4H En_MIND
CHAPTER 5 ETHERNET CONTROLLER
Table 5-1. Ethernet Controller's Register Categories
Offset Address
Table 5-2. MAC Control Register Map
R/W Access
R/W W
R/W W
R/W W
R/W W
R/W W
R/W W
- -
R/W W
- -
R/W W
R/W W
R W
- -
R/W W
R/W W
- -
W W
R/W W
R/W W
R W
R W
Preliminary User's Manual S15543EJ1V0UM
Register Categories
MAC Control Registers
Statistics Counter Registers
DMA and FIFO Management Registers
Interrupt and Configuration Registers
Description
MAC Configuration Register 1
MAC Configuration Register 2
Back-to-Back IPG Register
Non Back-to-Back IPG Register
Collision Register
Max Packet Length Register
Reserved for future use
Retry Count Register
Reserved for future use
Station Address Register 2
Station Address Register 1
Pause Timer Value Read Register
Reserved for future use
VLAN Type Register
MII Configuration Register
Reserved for future use
MII Command Register
MII Address Register
MII Write Data Register
MII Read Data Register
MII Indicator Register
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