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2.4.5.11 Virtual-to-physical address translation
During virtual-to-physical address translation, the CPU compares the 8-bit ASID (when the Global bit, G, is not set
to 1) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following comparisons
are also made:
In 32-bit mode, the high-order bits
VPN2 (virtual page number divided by two) of each TLB entry.
In 64-bit mode, the high-order bits
VPN2 (virtual page number divided by two) of each TLB entry.
If a TLB entry matches, the physical address and access control bits (C, D, and V) are retrieved from the matching
TLB entry. While the V bit of the entry must be set to 1 for a valid address translation to take place, it is not involved
in the determination of a matching TLB entry.
Figure 2-46 illustrates the TLB address translation flow.
Notes 1.
Up to bit 28. Number of bits depends on the TBL page size
2.
Up to bit 29. Number of bits depends on the TBL page size
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CHAPTER 2 V
4120A
R
Note 1
of the 32-bit virtual address are compared to the contents of the
Note 2
of the 64-bit virtual address are compared to the contents of the
Preliminary User's Manual S15543EJ1V0UM
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