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MULT
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
MULT rs, rt
Description:
The contents of general registers rs and rt are multiplied, treating both operands as signed 32-bit integer. No
integer overflow exception occurs under any circumstances.
In 64-bit mode, the operands must be valid 32-bit, sign-extended values.
When the operation completes, the low-order word of the double result is loaded into special register LO , and the
high-order word of the double result is loaded into special register HI .
If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct
operation requires separating reads of HI or LO from writes by a minimum of two other instructions.
Operation:
← undefined
32
T-2:
LO
← undefined
HI
← undefined
T-1:
LO
← undefined
HI
← GPR [rs] * GPR [rt]
T:
t
← t
LO
31...0
← t
HI
63...32
← undefined
64
T-2:
LO
← undefined
HI
← undefined
T-1:
LO
← undefined
HI
← GPR [rs]
T:
t
← (t
LO
31
← (t
HI
63
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Multiply
21 20
rs
rt
5
5
* GPR [rt]
31...0
31...0
32
)
|| t
31...0
32
)
|| t
63...32
Preliminary User's Manual S15543EJ1V0UM
16 15
0
0 0 0 0 0 0 0 0 0 0
10
MULT
6 5
0
MULT
0 1 1 0 0 0
6
533
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